Topics tagged UVM

Topic	Replies	Views	Activity
Configuring property using Field Automation macro UVM UVM , uvm_config_db , field-macros	2	20	May 19, 2024
Uvm_config_db set method clarification UVM UVM , uvm_config_db	1	108	May 17, 2024
Execution of connect phase twice in simulation UVM UVM , UVM-phases , phase-jump	14	2031	May 17, 2024
Issue with RAL Coverage bins creation UVM UVM , uvm-ral , ral_coverage	3	33	May 16, 2024
About new tech learning UVM SystemVerilog , UVM	0	43	May 10, 2024
Start AHB sequence based on AXI sequence response UVM UVM	0	42	May 10, 2024
Subordinated driver in agent UVM UVM	4	40	May 7, 2024
Why does the RAL read() update the mirrored AND desired register model values? UVM UVM , uvm-ral , Ral-write-and-read-methhods	3	2976	May 6, 2024
Randomization of beats SystemVerilog SystemVerilog , UVM	2	43	May 6, 2024
How can we verify a memory whose address location is swapped UVM UVM , memory-verification	19	10745	May 5, 2024
Uvm_sequencer usage UVM UVM	2	56	May 5, 2024
UVM Monitor the interface output, don't use the driver transaction - understanding this training recommendation UVM UVM , uvm-driver-monitor-transaction	2	171	May 4, 2024
While i am using backdoor access for memory model i am able to writing the data into memory while reading the data from back door throug uvm ral i am getting error as either path is invalid or you dont have PLI/ACC visibility for that object UVM UVM	1	43	May 4, 2024
Coverage collector or subscriber usage UVM UVM , Coverage	0	64	May 4, 2024
Overriding a parameter UVM UVM , parameter-override-class	9	14780	May 1, 2024
Have you heard? There's a new Academy course, Introduction to the UVM Announcements Announcements , UVM , Course , Ray-Salemi	0	1768	August 6, 2014
How to cover unsigned int UVM SystemVerilog , UVM , Coverage	1	70	April 30, 2024
How to set the config_db multiple times? UVM UVM	8	4724	April 26, 2024
Using uvm_config_db to register binded interfaces UVM UVM	4	71	April 21, 2024
Confusing UVM_ERROR in uvm_reg_bit_bash_seq UVM UVM , uvm_reg_bit_bash	4	1948	April 19, 2024
My interface detects output transation with 1 clk cycle delay SystemVerilog UVM	2	75	April 19, 2024
** Error: /vobs/ss_restart_vseq.sv(714): 'pass_ssr_vseq' is not a task name UVM UVM	3	51	April 18, 2024
[UVM/REG/DUPLROOT] There are 2 root register models named "reg_model". The names of the root register models have to be unique UVM SystemVerilog , UVM , uvm_reg , RAL-UVM	1	999	April 16, 2024
Function New Constructor UVM SystemVerilog , UVM	1	81	April 11, 2024
How do I avoid using #0 in an interface monitor SystemVerilog SystemVerilog , UVM	3	81	April 10, 2024
UVM RAL Register Name Access UVM UVM	4	71	April 8, 2024
DUT reference model location? UVM SystemVerilog , UVM	2	85	April 7, 2024
UVM RAL \| Errors in REG & RAL FILES UVM UVM	1	73	April 6, 2024
Memory usage keeps increasing as test runs UVM UVM	5	94	April 4, 2024
Reuse non-UVM classes in UVM environment UVM UVM	4	87	April 3, 2024