If the person who created ral files & reg model file, is mistakenly created with few errors and the scoreboard checkers are not throwing any errors for the data comparision?

How can someone know whether my UVM RAL model is created correctlty or not?

This is why you need a test plan that maps each setting in your registers with a functional test. And a test the test plan

For example, suppose you have a register that controls the rounding mode of floating point operations: truncate or round. You need to make sure you get the desired behavior for each setting, not just that the register has been set to each mode.

You could put in some error injection that puts the wrong setting for the mode you want and make sure it produces an error. (an error would be the passing behavior). However, this gets into the never ending “when am I done?” question.