Verification Academy

Topic	Replies	Views	Activity
Conditional operator in verilog SystemVerilog SystemVerilog , verilog-systemverilog	2	781	November 6, 2022
Synchronous assertion to check asynchronous reset SystemVerilog SystemVerilog	1	792	November 4, 2022
Back door access for uvm_mem UVM UVM	2	1288	November 4, 2022
Register Backdoor Issue UVM UVM , RAL , Cookbook-RegistersBackdoorAccess , UVM-RAL-Backdoor-Write-hdl_path	3	4080	November 4, 2022
How to increase cross coverage SystemVerilog SystemVerilog , Coverage-bins	0	380	November 4, 2022
Constraint SystemVerilog SystemVerilog	2	639	November 4, 2022
How to use queues of associative arrays? SystemVerilog SystemVerilog , queues-systemverilog	1	686	November 4, 2022
Uvm_sequence UVM UVM	1	351	November 3, 2022
Assertion is wrote is printing passing and failing log at same time stamp SystemVerilog SystemVerilog , assertion	1	960	November 3, 2022
Endpoint question SystemVerilog SystemVerilog	4	717	November 3, 2022
Does SystemVerilog allow to collect coverage on Testbench code? Coverage Coverage	4	2302	November 3, 2022
Regarding Driver internal signals in waveform UVM UVM	1	344	November 2, 2022
Accessing Multi dimension queue elements SystemVerilog SystemVerilog , System-Verilog	1	422	November 2, 2022
Valid and Invalid method() calls post lock_model() UVM UVM , Valid-and-Invalid-method-calls-post-lock_model	0	319	November 1, 2022
How to get count for a particular id in uvm in a test sequence UVM UVM , ID	2	592	November 1, 2022
Sequences started in parallel and how to use fork join_any if the number of sequences is varied? SystemVerilog SystemVerilog	4	808	November 1, 2022
Sequence library UVM UVM	4	902	November 1, 2022
Covert array into vector SystemVerilog SystemVerilog , vector-convert	4	1391	October 31, 2022
How to finish the forever until other component done? UVM UVM , uvm_objection , forever	3	694	October 31, 2022
Write code to execute task A in parallel 10 times, and call task B only after task A has finished executing 10 times SystemVerilog SystemVerilog	10	2105	October 31, 2022
Verilog logic pass multiple defines and simulate in a loop SystemVerilog SystemVerilog	2	641	October 31, 2022
Using inout ports in SVA properties/assertions SystemVerilog SystemVerilog , SVA , Inout-port	2	871	October 31, 2022
How to model axi slave transaction by using uvm framework? UVM UVM , axi-uvmf	0	568	October 31, 2022
Parameter not being recognized in transaction class SystemVerilog SystemVerilog , parameter , Package-interdependecy	2	617	October 30, 2022
Stop the simulation after N number of uvm_errors/assertions UVM UVM , xcelium	1	851	October 30, 2022
Pattern SystemVerilog SystemVerilog	5	962	October 30, 2022
System function '$sformatf' is invoked as task, its return value is discarded SystemVerilog SystemVerilog , system-function , sformatf	1	1742	October 29, 2022
How to reuse the agent , if multiple channels , let say 3 channels are present at phy layer? UVM UVM , mutilple-agent-for-the-same-bus-protcol	3	387	October 29, 2022
Write an assertion where in if a signal A goes high in one cycle, signals B and C should go low in the same cycle SystemVerilog SystemVerilog	2	1458	October 28, 2022
Why error when using process::self() in static task SystemVerilog SystemVerilog , Systemverilog-process	1	734	October 28, 2022