I am getting an error while accessing my dut register via backdoor as :-
UVM_ERROR: set: unable to locate hdl path (dut.reg1)
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
I have even used the set_backdoor method within the register model but If I use it I am getting the error
UVM_FATAL verilog_src/uvm-1.1d/src/reg/uvm_reg_backdoor.svh(329) @ 0: reporter [RegModel] uvm_reg_backdoor::write() method has not been overloaded
whenever I am using any access method from the sequence.
Hi Shreemant,
I have a bit of hands on experience using UVM RAL.
You need to set the HDL path in your register model using ,
add_hdl_path("The backdoor path from top
Mention your backdoor path here
", “RTL”);
lock_model();
And for each register in you model you need to specify the slice path using add_hdl_path_slice(Refer UVM user guide)
Once you define the paths you can start using backdoor write , in the same manner you do your frontdoor writes except that the argument path needs to be specified as .path(UVM_BACKDOOR).