Hi Shreemant,
I have a bit of hands on experience using UVM RAL.
You need to set the HDL path in your register model using ,
add_hdl_path("The backdoor path from top
Mention your backdoor path here
", “RTL”);
lock_model();
And for each register in you model you need to specify the slice path using add_hdl_path_slice(Refer UVM user guide)
Once you define the paths you can start using backdoor write , in the same manner you do your frontdoor writes except that the argument path needs to be specified as .path(UVM_BACKDOOR).
Hope this helps you.
Regards,
Jaswanth Ammineni