Pattern

SystemVerilog
1

How to generate a pattern 123454321

2

In reply to Vikas Misra:

rand bit [2:0] a[9];
constraint condition{foreach(a[i])
                       {if(i<=4)a[i]==(i+1);
                        else a[i] == (9-i);
                        }
                     }
3

In reply to Shubhabrata:
I written the code

class numbers_sequence;
 rand bit [2:0] numbers[9];
  constraint const_c { 
                      foreach(numbers[i])
                      {if(i<=4) numbers[i]==(i+1);
                       else numbers[i]==9-i;
          }  
                     }
endclass
 
module top;
  numbers_sequence o;
 
  initial
    begin
     o=new();
     o.randomize();
      $display("the numbers: %p",o.numbers);
    end
endmodule

but result
the numbers: '{1, 0, 7, 6, 5, 4, 3, 2, 1}

4

In reply to Vikas Misra:

For me, it’s working.
I am getting the required output.


class numbers_sequence;
rand bit [2:0] numbers[9];
constraint const_c {
foreach(numbers[i])
{if(i<=4) numbers[i]==(i+1);
else numbers[i]==9-i;
}
}
endclass

module top;
numbers_sequence o;

initial
begin
o=new();
o.randomize();
$display("the numbers: %p",o.numbers);
end
endmodule

Ouput :

vsim -voptargs=+acc=npr

run -all

the numbers: '{1, 2, 3, 4, 5, 4, 3, 2, 1}

exit

5

In reply to Vikas Misra:

It looks like the tool you are using has a bug using if/else in a constraint.

Use an implication instead of if/else. I prefer that anyways so my constraints do not look like procedural code.

  constraint const_c { 
    foreach(numbers[i]){
      i<=4 -> numbers[i]==(i+1);
      i>4 -> numbers[i]==9-i;
    }     
  }
6

In reply to dave_59:
Thanks Dave it is working.