Pattern

SystemVerilog
3

In reply to Shubhabrata:
I written the code

class numbers_sequence;
 rand bit [2:0] numbers[9];
  constraint const_c { 
                      foreach(numbers[i])
                      {if(i<=4) numbers[i]==(i+1);
                       else numbers[i]==9-i;
          }  
                     }
endclass
 
module top;
  numbers_sequence o;
 
  initial
    begin
     o=new();
     o.randomize();
      $display("the numbers: %p",o.numbers);
    end
endmodule

but result
the numbers: '{1, 0, 7, 6, 5, 4, 3, 2, 1}