Pattern

SystemVerilog
5

In reply to Vikas Misra:

It looks like the tool you are using has a bug using if/else in a constraint.

Use an implication instead of if/else. I prefer that anyways so my constraints do not look like procedural code.

  constraint const_c { 
    foreach(numbers[i]){
      i<=4 -> numbers[i]==(i+1);
      i>4 -> numbers[i]==9-i;
    }     
  }