Synchronous assertion to check asynchronous reset

SystemVerilog
1

Hi,

I want to do SVA checking on an asynchronous reset signal, if the reset is asserted the en signal must be 0 from the past 10 clock cycles before.

property(@(posedge clk) $fell(reset) |-> ($past(en,10) == 0));

The problem with the above snippet is the checking only happens on posedge of the clk but the reset is asynchronous which asserted non dependent to the clk. But the $past syntax wouldn’t have any clock reference if I didn’t put the clk.

Other than that, I believe this kind of way will affect the simulation performance.

If you guys have better way to suggest feel free to respond. Thanks in advance.

2

In reply to musyantsa:

  1. You can use the endpoint for en==0 for 10 cycles.
  2. First Synchronize the sync
    Edit code - EDA Playground

module m; 
  bit en, reset_sync, reset, clk; 
  sequence s_en; 
    @(posedge clk) en==0[*10];
  endsequence
    
  ap_reset_en: assert property(@(posedge clk) $fell(reset) |-> s_en.triggered);
    
  // Option: 1st synchonize the reset
  always @(posedge clk) reset_sync <= reset; 
  
  // Use en==0 for 10 clocks starting from the synced reset
  // Thus, you get 10+ clocks from the async reset
   ap_resetsync__en: assert property(@(posedge clk) $fell(reset_sync) |->
                                                   s_en.triggered);
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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