Conditional operator in verilog

SystemVerilog
,
1

assign MUX =
xx_r[0] ? { 1’d1, xx_r[3:2], ~xx_r[1] } : { 1’d0, xx_r[3:1] } ;
can someone explain this statement
thanks in advance

2

In reply to bellamarigo:


MUX = xx_r[0] ? { 1'd1, xx_r[3:2], ~xx_r[1] } : { 1'd0, xx_r[3:1] } ;
if(xx_e[0] 
    MUX= the concatenation of 1'd1, xx_r[3:2], ~xx_r[1]; 
else MUX = the concatenation of  1'd0, xx_r[3:1];
// For example, 
bit[3:0] MUX, xx_r; 
// with xx_r=1011; The assign yields MUX= 1100; 
// with xx_r=1010; The assign yields MUX= 0101;
3

In reply to ben@SystemVerilog.us:

thank you