Verilog logic pass multiple defines and simulate in a loop

SystemVerilog
1

Hi Dave,

I want to my verilog TB code to simulate by taking multiple defines in a loop fashion in a single run.

Example:
ifdef ATS_MEM_512_0001 fusel3mode = 4'b0101; //512 l3MemEn = 4'b0001; endif
ifdef ATS_MEM_1KB_0010 fusel3mode = 4'b0101; //512 l3MemEn = 4'b0010; endif
`ifdef ATS_MEM_512_0011
fusel3mode = 4’b0101; //512
l3MemEn = 4’b0011;

RUN command:
vcs code_sd_3.v tb_code_sd_1.v +define+ATS_MEM_010_1KB_0010
./simv +define+ATS_MEM_010_1KB_0010

Here instead of always passing different defines from my run command. i want to my TB to take all defines and run with each define in a iteration. Please help me with the logic for this.

like looping into each defines and run one after another in a single simulation.
+define+ATS_MEM_512_0001, ATS_MEM_1KB_0010, ATS_MEM_512_0011

Thanks and Regards,
Srikanth.P

2

In reply to srikanth.srivishnav:

`ifdef

is compiler directive and used for conditional compilation. Compiled code can’t be changed at run time.

3

In reply to srikanth.srivishnav:

The `ifdef is a compile time directive and can’t be changed at runtime.

If you want to use the same build for different values of ‘fusel3mode’ and ‘I3MemEn’, you can try forcing the values at runtime, but that may or may not work depending on the design.