Verification Academy

Topic	Replies	Views	Activity
'real' data type memory SystemVerilog SystemVerilog , Real-datatypes , bit_range , datatype , real	1	551	December 19, 2022
Need to randomise packed fixed array such that unique elements are generated and the elements are between 0 to 100 SystemVerilog SystemVerilog	1	456	December 17, 2022
Difference problem UVM UVM	1	312	December 17, 2022
Sensitivity list in task UVM UVM , sensitivity-list	8	1001	December 17, 2022
Evaluate each line in a file in systemverilog SystemVerilog SystemVerilog , System-Verilog	1	528	December 16, 2022
Is it possible to map 2 different sequencers to a reg_map one for read one for write? UVM UVM , uvm_reg_block , multiple-sequencers	18	1371	December 16, 2022
An Appropriate Folder Structure for Combined Design and Verification Version Control UVM UVM , System-Verilog , UVMF	1	720	December 15, 2022
Verilog design code for ETHERNET Protocol UVM UVM , UVM-Component-UVMTemplates-ReferenceDesign-UVMF , Ethernet , dut-design , ethernet-payload , Ethernet-UVM-Verification	1	1553	December 15, 2022
Functional coverage for associative array of enums Coverage Coverage , array-bins , associative-array	2	786	December 15, 2022
Disable with label is not working for while loop SystemVerilog SystemVerilog , disable-fork , fork_joinany	2	952	December 14, 2022
Self clearing logic with SystemVerilog SystemVerilog SystemVerilog , System-Verilog	4	1197	December 14, 2022
Soft Constraint Error while using with dist randomisation SystemVerilog SystemVerilog	1	395	December 13, 2022
Accurate clock generator SystemVerilog SystemVerilog , clock-frequency , Timescale , Clock-Generation	1	564	December 13, 2022
Compare unpacked array in constraint SystemVerilog SystemVerilog , constraint	1	520	December 13, 2022
Use store sequence transaction in fetch sequence UVM UVM , UVM-sequence-sequencer-nested_sequence-transaction	1	340	December 13, 2022
Uvm_reg_indirect_data UVM UVM	0	234	December 12, 2022
Assertion failed with delay operator SystemVerilog SystemVerilog , assertion	5	745	December 12, 2022
Understanding SystemVerilog Scheduling better SystemVerilog SystemVerilog	3	987	December 12, 2022
UVM Sequence_Item Constraint for increase 1 UVM UVM , uvm_sequence_item , constraint-randomization , Increase-one	2	543	December 12, 2022
Uvm testbench UVM UVM	1	350	December 12, 2022
Debug Query UVM UVM , Debug	3	641	December 12, 2022
Trigger other check SystemVerilog SystemVerilog	3	643	December 12, 2022
Is there a "$sincos" function/task in SV? SystemVerilog SystemVerilog , UVM-sine-wave	1	531	December 11, 2022
How to create a sine wave generator module? SystemVerilog SystemVerilog , UVM-sine-wave	0	934	December 11, 2022
Dynamic array concatenation problem SystemVerilog SystemVerilog , interface , dynamic	3	948	December 10, 2022
Why can an interface be recognized in a package, but a class cannot SystemVerilog SystemVerilog , Package	2	1259	December 10, 2022
Import declaration in SV/UVM SystemVerilog SystemVerilog	1	627	December 10, 2022
Command line arguments inside a sequence UVM UVM , Command-line-arguments-inside-a-sequence	4	2412	December 10, 2022
Is there any open source project, which has a good usage of UVM&SV UVM UVM	0	381	December 9, 2022
Signal delay by X clock cycles in System Verilog SystemVerilog SystemVerilog , Verilog , Delay , clock , signal	5	24363	December 9, 2022