Accurate clock generator

SystemVerilog
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1

Hi,

I want to generate a 875Mhz clock (this means a 1.142857143e-9 time period).
I do this by:

initial begin
    int clk_cycle_fs = int'(1_000_000_000.0/875.0);
    #(1fs * (clk_cycle_fs/2))
    clk = 1;
    #(1fs * (clk_cycle_fs/2))
    clk = 0;
  end

In simulation i get time period of 1.142858e-9. that means 874.999343Mhz clock, and not the clock i want.
does anyone know why this is the generated clock? is the simulation not accurate enough? is there other way of getting 875Mhz clock?

I use `timescale 100ps/1ps inside tb.

2

Hi oglick,

To achieve an 875Mhz clock, you need 1.142857143ns, equal to 1142.857143ps and 1142857.143fs. Since fs is the smallest timescale unit, I believe 1142858fs(=874.999344Mhz) would be the closest you can get.