UVM Sequence_Item Constraint for increase 1

UVM
, , ,
1

Hi, When I use

constraint c_state == const'(state) +1;

in sequence_item the value gives undefined. However when I use

constraint c_state { state == 1;}

it gives 1 or which value I wrote there. What is the way that I can increase the value of state 1.


class alu_sequence_item extends uvm_sequence_item;
  `uvm_object_utils(alu_sequence_item)

  rand logic i_rst;
  rand logic [15:0] i_memData;
  
  logic [15:0] o_memData; //output
  logic [5:0] o_memAddr; //output
  bit o_memWrEnable; // output
  
  rand logic [1:0] state;
	
  constraint c_state { state == 1;} //Here is the problem
  
  function new(string name = "alu_sequence_item");
    super.new(name);
    
  endfunction: new

endclass: alu_sequence_item

I have checked using uvminfo if there is a problem in my interface or sequence but no if I dont write any constrait then it generates random 2 bit values in scoreboard.

I need help to increase it one every clock cycle. Thank you.

2

In reply to DenizGuzel:

I believe you mean state should be increased for each seq_item.
You can do this in the sequence where you are calling your seq_item like this

task body();
   your_item.state = 1;
   for (int i = 0; i < max_items; i++)
     uvm_do_with (your_item, {your_item.state + i;})
endtask
3

In reply to chr_sue:

Thank you sir.