Uvm testbench

UVM
1

I had written the below code for the traffic lights as it is compile free but could not able to get the correct output . the link and the design is given below Error

2

Your sequences randomizes the transaction.
your transaction has the following code which means the ‘count’ is randomizable

================
**class transaction extends uvm_sequence_item;
// bit clk;
rand bit [1:0] count;
…
constraint dist1 { count dist {2’b01:=40, 2’b00:=30, 2’b10:=30};}
**

So you are producing random counts in the range 0-2 with the distribution you specified in the constraint.

Is the DUT not expecting the count to increment 0,1,2,0,1,2, etc ?
Try using randc for ‘count’
randc bit [1:0] count;

then change constraint to :
constraint dist1 { count < 2’b11;}

Hope that helps