Browse all content in Siemens Verification Academy with the tag gate-level

September 2024

• Challenges of Multiple FPGA Tool Flow Verification

  FPGA Verification Sep 18, 2024 Paul Bobko - Westinghouse Electric pdf

October 2023

• Questa Signoff CDC Fact Sheet

  Questa Design Solutions Oct 01, 2023 pdf

September 2022

• Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs

  Formal Verification Sep 30, 2022 Martin Rowe Webinar

May 2021

• The Three Witches Preventing Glitch Nightmares on CDC Paths

  Clock-Domain Crossing May 18, 2021 Ping Yeung pdf

March 2021

• I Didn’t Know Visualizer Could Do That

  Debug Mar 30, 2021 Rich Edelman Webinar

• Preventing Glitch Nightmares on CDC Paths

  Clock-Domain Crossing Mar 26, 2021 Ping Yeung Webinar

• Preventing Glitch Nightmares on CDC Paths

  Clock-Domain Crossing Mar 26, 2021 Ping Yeung pdf

June 2019

• Reusable UPF - Transitioning from RTL to Gate Level Verification

  Low Power Jun 11, 2019 pdf

February 2019

• Efficient Modeling Styles and Methodology for Gate-Level Design Verification

  Questa Design Solutions Feb 28, 2019 Rohit Jain Paper

• Efficient Modeling Styles and Methodology for Gate-Level Design Verification

  Questa Design Solutions Feb 28, 2019 Rohit Jain pdf

July 2018

• No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

  Questa Design Solutions Jul 26, 2018 Kurt Takara mp4

June 2017

• RTL CDC Is No Longer Enough — How Gate-Level CDC Is Now Essential to First Pass Success

  Clock-Domain Crossing Jun 29, 2017 Joe Hupcey Article