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November 2023

Hierarchical verification flow for FPGA design projects
Formal Verification Nov 16, 2023 Mamma Benmoussa Garsault - Arcys mp4
How to sign-off cryptographic hash implementations with generated formal assertions
Formal Verification Nov 16, 2023 Tobias Ludwig - Lubis Eda mp4
Debugging enhancements for formal property checking
Formal Verification Nov 16, 2023 Holger Busch - Infineon mp4
osmosis 2023
Formal Verification Nov 16, 2023 Nicolae Tusinschi Conference
Prevent Performance Problems with Prompt RTL Profiling
Debug Nov 09, 2023 Rich Edelman Webinar

October 2023

Smart Verification, Faster is not enough!
Machine Learning Oct 30, 2023 Harry Foster pdf
Verify designs created in MATLAB or Simulink within subsystem or full-chip UVM simulations
UVM Framework Oct 30, 2023 Bob Oden pdf
When it Comes to Artificial Intelligence and Machine Learning, Siemens Has You Covered
Machine Learning Oct 30, 2023 Tom Fitzpatrick pdf
Industry Trends in Functional Verification!
Planning, Measurement and Analysis Oct 30, 2023 Harry Foster pdf
Success with Continuous Integration and Continuous Development (CI/CD) Pipeline using automated checking
Questa Design Solutions Oct 30, 2023 Afzal Usmani - Siemens Eda pdf
MARLUG - 2023
Machine Learning Oct 30, 2023 Harry Foster Seminar
Selective hardening in space applications
Functional Safety Oct 24, 2023 Jacob Wiltgen link
Starting Your UVM Simulation
UVM - Universal Verification Methodology Oct 10, 2023 Chris Spear link
Selective Radiation Mitigation for Integrated Circuits
Functional Safety Oct 09, 2023 Jacob Wiltgen Paper
Selective Radiation Mitigation for Integrated Circuits
Functional Safety Oct 09, 2023 Jacob Wiltgen pdf
Questa Formal Apps Fact Sheet
Formal Verification Oct 01, 2023 link
Questa Verification IQ Fact Sheet
Verification IQ Oct 01, 2023 pdf
Questa RDC Fact Sheet
Reset-Domain Crossing Oct 01, 2023 pdf
Questa Lint Fact Sheet
Questa Design Solutions Oct 01, 2023 pdf
Austemper Analysis and Fault Simulation
Functional Safety Oct 01, 2023 pdf
QuestaSim Fact Sheet
Simulation Oct 01, 2023 pdf
Questa Verification IQ Fact Sheet
Verification IQ Oct 01, 2023 pdf
Questa Signoff CDC Fact Sheet
Questa Design Solutions Oct 01, 2023 pdf
Questa Visualizer Fact Sheet
Debug Oct 01, 2023 pdf
Questa Verification IP Fact Sheet
Verification IP Oct 01, 2023 pdf

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Browse all content in Siemens Verification Academy with the tag junit

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