Verification Academy

Topic	Replies	Views	Activity
Welcome to our Verification Academy community! Announcements	1	229	September 13, 2023
How can we verify a memory whose address location is swapped UVM UVM , memory-verification	19	10691	May 5, 2024
Uvm_sequencer usage UVM UVM	2	14	May 5, 2024
Seq_item_port driver-sequencer - communication issue UVM	2	13	May 5, 2024
Using goto repetition SystemVerilog SystemVerilog , Using-goto-repetition	4	280	May 4, 2024
Discrepancy on legality of the consequent SystemVerilog SystemVerilog , SVA , system-verilog-assertion-SVA , SVA-Assertion	7	58	May 4, 2024
UVM Monitor the interface output, don't use the driver transaction - understanding this training recommendation UVM UVM , uvm-driver-monitor-transaction	2	140	May 4, 2024
While i am using backdoor access for memory model i am able to writing the data into memory while reading the data from back door throug uvm ral i am getting error as either path is invalid or you dont have PLI/ACC visibility for that object UVM UVM	1	18	May 4, 2024
Overriding UVM_NONE messages UVM UVM-Reporting	4	19	May 4, 2024
Testbench problem with simple stream cipher SystemVerilog	0	10	May 4, 2024
Tackling a constraint in post_randomize() SystemVerilog constraint-randomization , systemverilog-constraint	2	33	May 4, 2024
Could you please clarify in which region clocking block posedge of clock is executed SystemVerilog	3	27	May 4, 2024
Coverage collector or subscriber usage UVM UVM , Coverage	0	11	May 4, 2024
Setting a word-length parameter using $bits on struct field SystemVerilog	1	22	May 3, 2024
Is clocking block driving logic is equivalent to the following? SystemVerilog	1	27	May 2, 2024
Smart way to bundle up multiple RTL signals when passing to monitor SystemVerilog SystemVerilog , UVM-monitor	1	27	May 2, 2024
Overriding a parameter UVM UVM , parameter-override-class	9	14741	May 1, 2024
Uvm sequence body does not start after completion of base sequence pre_body UVM	3	30	May 1, 2024
Uvm_reg_data_t constraint randomization UVM	2	33	May 1, 2024
SVA - fundamental questions SystemVerilog SVA-Assertion , SVA-checkers , SVA-Assertion-Systemverilog	5	25	May 1, 2024
Randc variable randomization inside top sequence class SystemVerilog SystemVerilog , constraint-randomization , randomization , randc-usage-constraint , systemverilog-constraint	3	26	May 1, 2024
Analysis Port Write functionality UVM analysis-port , analysis-export	1	23	April 30, 2024
Web Seminar - Beyond UVM: Effectively Modeling and Analyzing Coverage Announcements Announcements , Web-Seminar , Verification-Cookbook	0	3543	November 21, 2012
Introducing the Coverage Cookbook Coverage Coverage	1	4077	March 19, 2013
UVM/OVM Recipe of the Month - Intro to UVM Registers Announcements Announcements	0	5679	October 4, 2011
Have you heard? There's a new Academy course, Introduction to the UVM Announcements Announcements , UVM , Course , Ray-Salemi	0	1757	August 6, 2014
How to cover unsigned int UVM SystemVerilog , UVM , Coverage	1	41	April 30, 2024
Web Seminar Notification: New School Thinking for Fast and Efficient Verification Using EZ-VIP Announcements Announcements , Verification-Academy-Technology-Series , Verification-IP	0	1580	April 20, 2015
Web Seminar Notification: New School Coverage Closure Announcements Announcements , Verification-Academy-Technology-Series , Questa-CoverCheck	0	1550	May 20, 2015
SystemVerilog Hiearchial Reference to UUT Internal Signal? SystemVerilog SystemVerilog	2	26	April 30, 2024