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by Nikhil Jain, Mentor Graphics
This article describes how Mentor's verification IP (VIP) for various double-data rate (DDR) memory standards can act as a bus monitor and help yield fast, flexible verification and easy debugging. We discuss how to boost productivity using the inbuilt coverage collector and checking assertions by passively monitoring data on the bus. Mentor provides verification IP that spans multiple engines; simulation, formal and acceleration (emulation) allowing effective test re-use from simulation through to acceleration, but the article focuses on simulation using Questa Verification IP.
OVERVIEW
Verifying and debugging DDR SDRAM memory designs is challenging because of the speed and complex timing of the signals
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