As FPGAs grow in size and complexity managing and leading FPGA verification is becoming a challenging task. Verification planning and functional coverage gives leads and managers the tools they need to maintain perspective on projects. Using concrete metrics to track progress increases the quality of the design, identify problem areas early, and ensure better schedule predictability. This session explores how to ensure that debug and verification is done in the most effective place by using block benches, chip benches, formal tools, and lab test appropriately.
What You Will Learn
- How verification planning enables higher quality FPGAs and speeds up debugging
- What functional coverage is and how it helps teams maintain perspective during development
- How data driven verification improves schedule predictability and identifies problem areas early
