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Automate UVM Register Models

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UVM Register Assistant Session | Subject Matter Expert - Tom Fitzpatrick | UVM Recipe of the Month Seminar

Session Details

The UVM Register Layer is a great way to abstract the interaction between your testbench and your DUT from the pin-level, or even protocol-specific transactions to a generic register-based view of communication. This abstraction provides many benefits, not the least of which is isolating your stimulus generation and coverage modeling from low-level changes in your design (i.e. separating the what from the how). Unfortunately, the benefits of using the register layer come at the cost of having to specify the register models in your testbench to reflect the registers in your hardware. With thousands or even tens of thousands of registers in a typical design, this can be a laborious and error-prone process when done from scratch.

This Verification Cookbook seminar will introduce the UVM Register Assistant showing how to generate correct-by-construction register models and tests from a register specification.