Search Results

5 Results

• Portable Stimulus and VIP: Like a Hand in a Glove

  Resource (Verification Horizons Blog) - Aug 08, 2024 by Tom Fitzpatrick

  Many of you know that I am particularly passionate about the Portable Stimulus Standard (PSS) and wanted to let you know that my recording of “Portable Stimulus and Verification IP Fit Together Like a Hand in a Glove” is now available on Verification Academy .

• Introducing Smart Verification: Unleashing the Potential of AI Within Functional Verification

  Conference - Jun 24, 2024 by Tom Fitzpatrick

  In this session, you will learn that leveraging the power of AI and ML, Smart Verification revolutionizes functional verification by using faster engines that complement traditional heuristics with machine learning. Allowing engineers to be more productive with advanced creation, analysis, and debugging capabilities, while reducing workloads through predictive technologies that streamline and accelerate the verification process.

• Accelerated Confidence in Interface Designs mixing Software Layers, Hardware Protocols, Physical Connections

  Conference - Jun 24, 2024 by Gordon Allan

  In this session, you will learn that today high performance compute fabrics are spread over multiple die, multiple packages, multiple cards and racks in the data center. They are linked together by layers of CPU-to-CPU, cache-to-cache, and network node-to-node infrastructure. Those connections are based on standardized protocols, always evolving and improving, and increasingly having both a hardware interaction of multiple layers, plus one or more software layers.

• Portable Stimulus and Verification IP Fit Together Like a Hand in a Glove

  Conference - Jun 24, 2024 by Tom Fitzpatrick

  In this session, you will learn that the Portable Stimulus Standard (PSS) encourages verification engineers to focus on describing test scenarios, without worrying about the underlying target environment on which the test will ultimately be run. By describing the scenarios in terms of a randomizable schedule of actions, or behaviors that will execute, the test can easily be retargeted to different implementations for different environments.

• Challenges of Developing IPs for AI Chips

  Conference - Jun 24, 2024 by Tom Fitzpatrick

  Tom Fitzpatrick interviews Rambus VP of Engineering Susheel Tadikonda about the high-level D&V challenges of developing IPs for the new breed of AI accelerator chips; including the need to support a high-degree of IP configurability, 3DIC-specific protocol requirements that call for new levels of security for data in-motion and at rest.