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62 Results

• Wishbone SoC Testplan

  Resource (Reference Documentation) - Dec 04, 2013 by Verification Methodology Team

  Wishbone SoC testplan spreadsheet example (.zip)

• System Level Functional Coverage Example

  Chapter - Dec 04, 2013 by Harry Foster

  System level functional verification can take full advantage of the fact that the entire design is a self contained unit that will be used by customers, and thus has some logical use model that the customer will follow. Also, being a system, often it is made up of trusted IP, and the verification focus is aimed more at the block interconnect and any new functionality.

• APB3 Protocol Monitor

  Chapter - Dec 04, 2013 by Harry Foster

  The APB3 Protocol Monitor is passive and intended to be a reuseable verification component. Therefore, it is parameterized to allow it to be used with different bus widths and all of the signals on the port interface are inputs.

• Design For Analysis

  Chapter - Dec 04, 2013 by Harry Foster

  Taking care with the implementation of covergroups is an investment in time that can pay back when you or someone else need to understand where the missing functional coverage is.

• Coverage Cookbook

  Resource (Cookbook) - Dec 04, 2013 by Harry Foster

• Monitors, Monitors Everywhere – Who Is Monitoring the Monitors

  Article - Jun 01, 2013 by Rich Edelman

  The reader of this article should be interested in predicting or monitoring the behavior of his hardware. This article will review phase-level monitoring, transaction-level monitoring, general monitoring, in-order and out-of-order transaction-level monitors, A protocol specific AXI monitor written at the transaction-level of abstraction will be demonstrated. Under certain AXI usages, problems arise.

• System Level Code Coverage using Vista Architect and SystemC

  Article - Feb 22, 2013 by Ken P. McCarty - Siemens EDA

  SoC are constantly becoming more and more complex forcing design teams to eke out as much performance as possible just to stay competitive. Design teams need to get it right from the start and can't wait until it's built to find out how it truly performs. This is where System Level Modeling and SystemC/TLM shine.

• Monitors, Monitors Everywhere – Who Is Monitoring the Monitors

  Resource (Technical Paper) - Feb 07, 2013 by Rich Edelman

  In a verification environment the task of a monitor is to monitor activity on a set of DUT pins. This could be as simple as looking at READ/WRITE pins or as complex as a complete protocol bus, such as AXI or PCIe. In a very simple case a monitor can be looking at a pin or a set of pins and generating an event or raising a flag every time there is a change in signal values. The flag or event can trigger a scoreboard or coverage collector to perform an activity.

• Monitors, Monitors Everywhere – Who Is Monitoring the Monitors

  Paper - Feb 07, 2013 by Rich Edelman

  This paper will review phase-level monitoring, transaction-level monitoring, and general monitoring. In-order and out-of-order transaction-level monitors and UVM constructs for single and multiple port monitors will be demonstrated, including discussion about simple function implementations versus FIFO and threaded implementations. A protocol specific AXI monitor written at the transaction-level of abstraction will be demonstrated.

• Effectively Modeling and Analyzing Coverage

  Webinar - Nov 15, 2012 by Tom Fitzpatrick

  In this session, we will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret.

• Scoreboards and Results Predictors in UVM

  Webinar - Sep 17, 2012 by Tom Fitzpatrick

  In this session, you will learn how to outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.

• FPGA Verification Capabilities

  Track - Aug 30, 2012 by Ray Salemi

  This track introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.