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Formal 101 – Setting Up & Optimizing Constraints
Session - May 10, 2021 by Mark Eslinger
In this session we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints themselves, your test plan and formal coverage plan, and the DUT behavior.
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Setting Up & Optimizing Constraints
Resource (Slides (.PDF)) - May 10, 2021 by
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Optimizing a Fault Campaign for Complex Mixed-Signal Devices
Webinar - May 04, 2021 by Jacob Wiltgen
In this session, you will learn details how to effectively set up and execute an ISO 26262 fault campaign for mixed signal designs and establishing an efficient fault injection workflow for analog and digital portions of the design.
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Low Power Considerations for Verification
Webinar - Apr 29, 2021 by Rick Koster
Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. In this session we will discuss how to use these commands to manage verification.
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Formal 101 – Basic Abstraction Techniques
Session - Apr 21, 2021 by Jin Hou
In this session we will teach about the types of DUT constructs that commonly cause trouble for the formal analysis, and how to apply time-tested techniques to safely abstract them away so that the formal verification run can rapidly reach closure.
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A Methodology for Comprehensive CDC+RDC Analysis
Resource (Slides (.PDF)) - Apr 20, 2021 by Kurt Takara
In this session, you will learn how to improve your comprehensive CDC and RDC methodology development schedules and predictability.
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A Methodology for Comprehensive CDC+RDC Analysis
Webinar - Apr 20, 2021 by Kurt Takara
In this session, you will learn how to improve your comprehensive CDC and RDC methodology development schedules and predictability.
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Easy Test Writing with a Proxy-driven Testbench
Webinar - Apr 06, 2021 by Ray Salemi
In this session we'll examine ways to create powerful reusable testbenches by hiding the signals and providing your test writers with a proxy that lets them start writing tests immediately.
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Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog
Resource (Paper (.PDF)) - Mar 31, 2021 by
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Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog
Resource (Paper (.PDF)) - Mar 31, 2021 by
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Early Design Validation AI Accelerator’s System Level Performance Using An HLS Design Methodology
Resource (Slides (.PDF)) - Mar 31, 2021 by Michael Fingeroff - Siemens EDA
This workshop will demonstrate how pre-hls simulation using MatchLib can identify and fix potential system-level performance issues that are normally not found till very late in a hand-coded RTL design methodology.
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Early Design & Validation of an AI Accelerator’s Performance Using an HLS Design
Seminar - Mar 31, 2021 by Michael Fingeroff - Siemens EDA
This workshop will show how an HLS design and verification flow built around Catapult, and the ecosystem around it, could dramatically speed up the design of the AI/ML hardware accelerators compared to a traditional RTL based flow. It will focus on using the open-source MatchLib SystemC library from NVIDIA to perform rapid modelling and synthesis of the ML accelerator.
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Functional Debug: Verification and Beyond
Webinar - Mar 31, 2021 by Hanan Moller
In this session, we will discuss the features of functional debug solutions and the benefits they bring throughout the SoC development process.
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Making Your DPI-C Interface a Fast River of Data
Webinar - Mar 31, 2021 by Rich Edelman
This session will describe DPI-C usage, including imported calls, exported calls, context calls, input, output and inout arguments, call-by-reference and return values. This will be a good reference for beginners but also containing tips and advanced usage for the current DPI-C user.
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Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Webinar - Mar 31, 2021 by Progyna Khondkar
This session distinctively studies the ‘simulation-impacting’ features of ‘design top’ IOs and the effect of each feature on verification results; this has been accomplished by thoroughly identifying every possible scenario for different design tops, their port types, possible LRM interpretations, presence of design or liberty or UPF attributes, and repercussions at post synthesis simulation.
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Functional Debug: Verification and Beyond
Webinar - Mar 31, 2021 by Hanan Moller
In this session, we will explore an alternative approach to SoC development, analysis, debug and bring up. We will describe a different approach, in which debug and performance tuning is considered from the outset, by including within the SoC a light but independent infrastructure dedicated to bringing debug visibility across the entire SoC – an approach which is independent of CPU architecture.
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Bringing Reset and Power Domains Together – Confronting UPF Instrumentation
Webinar - Mar 31, 2021 by Abdul Moyeen
This session specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time.
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Making Your DPI-C Interface A Fast River Of Data
Resource (Slides (.PDF)) - Mar 31, 2021 by Rich Edelman
DPI-C is a powerful way to integrate C code with SystemVerilog. The interface is a simple function or task call, identical to a normal SystemVerilog function or task call. This paper will describe DPI-C usage, including imported calls, exported calls, context calls, input, output and inout arguments, call-by-reference and return values. This will be a good reference for beginners but also containing tips and advanced usage for the current DPI-C user.
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Making Your DPI-C Interface A Fast River Of Data
Resource (Paper (.PDF)) - Mar 31, 2021 by Rich Edelman
SystemVerilog DPI-C enables functional verification teams to leverage C code for modeling, checking and utility functions. The simple "C" style call interface allows fast adoption and easy integration. This paper explains the workings of the integration and provides data type mapping examples and some hints on optimizing the calls for maximum performance.
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“Bounded Proof” Sign-Off with Formal Coverage
Webinar - Mar 31, 2021 by Joe Hupcey
In this session, we will show how “Formal Coverage” methodologies and the resulting data enable engineers to effectively judge the quality of verification that these “bounded proofs” provide.
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Handling Reset Domain Crossing for Designs with Set-Reset Flops
Webinar - Mar 31, 2021 by Abdul Moyeen
This session specifically explores the different possible scenarios with such flops and problems introduced by these in the RDC closure. Which potentially can be dangerous and time consuming.
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Handling Reset Domain Crossing for Designs with Set-Reset Flops
Resource (Slides (.PDF)) - Mar 31, 2021 by Abdul Moyeen
There are cases where the Reset Domain definition is not that simple and straight forward. One such case is the handling of “Set-Reset” flops. We face design structures where there are more than one asynchronous set/reset controlling a flop. Then there can be scenarios involving data transfer between two such flops. Another matter of concern is if the output of such flops is used as reset further down the design.
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Handling Reset Domain Crossing for Designs with Set-Reset Flops
Resource (Paper (.PDF)) - Mar 31, 2021 by Abdul Moyeen
There are cases where the Reset Domain definition is not that simple and straight forward. One such case is the handling of “Set-Reset” flops. We face design features where there is more than one asynchronous set/reset controlling a flop. This paper specifically explores the different possible scenarios with such flops and problems introduced by these in the RDC closure. Which potentially can be dangerous and time consuming.
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Handling Reset Domain Crossing for Designs with Set-Reset Flops
Resource (Paper (.PDF)) - Mar 31, 2021 by Abdul Moyeen
Reset domain Crossing has emerged into a major and un-avoidable design step in modern ASIC design flows. In any Digital design, Reset Domain Crossing (RDC) is essentially a structure where a signal crosses over from one reset domain to another reset domain. In this paper we will try to look at the problem structurally and propose a strategy to reach a conclusion where we face such design structures.
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Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Resource (Slides (.PDF)) - Mar 31, 2021 by Progyna Khondkar
Top level primary IOs remain mysterious in the verification world, specifically when you consider UPF-based low power designs. In real silicon, they are usually driven by off-chip supplies; however, verification complications multifold at RTL and gate-level simulations for them.