Search Results
Filters
Advanced Search
2075 Results
-
How to Use Checklists for DO-254 Verification
Resource (Verification Horizons Blog) - Jul 07, 2022 by Tammy Reeve - Patmos Engineering Services
Document DO-254 provides aerospace and defense companies with the needed guidance to develop and verify airborne electronic hardware. Some clients use products like Siemens’ Questa to fulfill vital verification objectives of DO-254 such as hardware behavior simulation and code coverage as a means for elemental analysis. But did you know a simple checklist can also be an effective DO-254 verification tool?
-
Back to the Future with Formal Property Checking
Article - Jul 05, 2022 by Harry Foster
Back in 2010, I decided that instead of documenting a specific instance of applying formal property checking on a particular design, I would step back and look at the formal property checking process holistically. The goal was to define a set of repeatable steps that could be applied to any design. Fast forward to today, where I update the original by keeping the content that is still relevant and augmenting it with the new philosophies, methodologies, and technologies that have evolved since.
-
The Democratization of Digital Methodologies for AMS Verification
Article - Jul 05, 2022 by Sumit Vishwakarma
A mixed-signal design is a combination of tightly interlaced analog and digital circuitry. Next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern systems on chips (SoCs). There are two critical reasons for this trend.
-
Getting to Know Visualizer - Part II
Article - Jul 05, 2022 by Rich Edelman
Welcome to part 2 of our overview of the Visualizer Debug Environment, the user interface to debug, analyze and verify all our Siemens functional verification tools. As we saw in part 1 , Visualizer is first and foremost a waveform debugger, with a host of other powerful debug capabilities also provided and supporting Verilog, SystemVerilog, VHDL, System C and C/C++. In this part of the article, we’ll look at driver tracing, X tracing, schematics, glitch debug, low power debug and more.
-
Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces
Article - Jul 05, 2022 by Himani Kaushik - Siemens EDA
Since the advent of digitalization, there has been an exponential growth in the volume of data. With this boost in the amount of data, hard disk drives (HDDs) could not sustain the data transfer rates, leading to bottlenecks in data access. Solid state drives (SSDs) have come to the forefront as a promising solution to our modern-day storage demands. SSDs are constantly evolving with upgrades of their critical components to provide high access speeds.
-
Bringing 5G NR Radio Frame Generation and Analysis to the Veloce® X-STEP™ Product Family
Article - Jul 05, 2022 by Yrjö Keränen - Siemens EDA
Booming worldwide development activities for 5G NR create an increasing need for reference data and signal analysis. Recently launched Veloce X-STEP IQ Toolset (IQT) provides 3GPP compliant test data for radio unit (RU) testing needs. IQT workflow integrates with Siemens EDA tools such as Questa, Veloce and X-STEP. Being a standalone software solution, it is a cost-efficient solution to be installed in multiple workstations.
-
Speeding OTN Verification Using Emulation
Article - Jul 05, 2022 by Pradeep Gupta, Saurabh Khaitan - Siemens EDA
In today's connected world, bandwidth requirements have shot up drastically due to the exponential growth in data communication. Optical Transfer Networks (OTN) today are the backbone of the tremendous amount of worldwide internet traffic. The ITU-T standards committee developed the OTN standard to address this data explosion with reliable infrastructure and low transmission costs in the optical world.
-
Reflections on Users’ Experiences with SVA - Part II
Article - Jul 05, 2022 by Ben Cohen
During my years of contributions to the Verification Academy SystemVerilog Forum, I have seen many trends in real users’ difficulties in the application of assertions, and misunderstandings of how SVA works. In Part 1 of this article, I addressed the difficulties in expressing requirements for assertions, and clarified some critical SVA concepts concerning terminology, threads, and vacuity.
-
Easy Testbench Speedups
Article - Jul 05, 2022 by Eileen Hickey - Doulos Inc.
As a Doulos ‘techie’, I train over 100 engineers in SystemVerilog and UVM each year. I do believe quite soundly, that the effort of simulation verification is an art, supported by the language. So, regardless of the language, I have a ready list of useful testbench coding strategies to achieve faster regression CPU cycle execution. This means more regression tests executed in the same amount of ‘wall-clock’ time!
-
Functional Safety Verification Challenges for Automotive ICs
Article - Jul 05, 2022 by Mihajlo Katona - Veriest
In a semiconductor world, functional safety is all about data storage and data movement through the system. Electrical or magnetic interference inside hardware systems can cause a single bit to flip to the opposite state spontaneously. And this is a typical case for random failure, which we desperately need to analyze and see its effects on the functional behavior of the system we are verifying.
-
The Path to a Safety Mechanism on an Unsafe PCIe® Sub-Module
Article - Jul 05, 2022 by Avnita Pal - Silicon Interfaces
This article illustrates the implementation of Safety Mechanisms on an unsafe PCIe® sub-module and demonstrates the use of Siemens EDA Austemper tools to generate Alarms for fault list detection and ensure Safety using a Duplication Mechanism.
-
Questa Lint vs Formal AutoCheck
Webinar - Jun 15, 2022 by Kevin Campbell
In this session, you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.
-
Questa Lint vs Formal AutoCheck
Resource (Slides (.PDF)) - Jun 15, 2022 by Kevin Campbell
In this session, you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.
-
The Three Pillars of Intent-Focused Insight
Webinar - Jun 08, 2022 by Harry Foster
This session reviews the impact of today’s verification crisis, identifies the fundamental problem contributing to this crisis, and then prescribes a solution.
-
Advanced Debug Techniques
Track - May 23, 2022 by Rich Edelman
In this track, you will learn how the Visualizer Debug Environment can debug and verify your complex SoCs and FPGAs.
-
UVM Connect
Track - May 23, 2022 by Adam Erickson
UVM Connect will demonstrate how to reuse your SystemC architectural models and/or reuse SystemVerilog UVM agents to verify models in SystemC.
-
SystemVerilog OOP for UVM Verification
Track - May 23, 2022 by Dave Rich
The SystemVerilog OOP for UVM Verification is aimed at introducing the OOP features in SystemVerilog most commonly used by the UVM in the simplest form.
-
Advanced UVM
Track - May 23, 2022 by Tom Fitzpatrick
Advanced UVM builds upon the concepts covered in Basic UVM to take your UVM understanding to the next level.
-
Introduction to the UVM
Track - May 23, 2022 by Tom Fitzpatrick
Advanced UVM builds upon the concepts covered in Basic UVM to take your UVM understanding to the next level.
-
Verilog & VHDL Debug & Weeding
Resource (Verification Horizons Blog) - May 18, 2022 by Rich Edelman
Verilog and VHDL Debug can get tedious trying to find causality. In this BLOG we discuss automation that can improve your productivity.
-
Aerospace and Defense Verification Tech Day
Track - May 11, 2022 by Joe Hupcey
Join Siemens EDA as we share an engineering update on the methodologies, technologies, and solutions for the ASIC, FPGA, and systems verification challenges unique to today’s Aerospace and Defense industry. Design and verification engineers and managers serving the Aerospace and Defense industry won’t want to miss this deep dive into the future of digital verification.
-
Siemens and the US Government - Mitigating Microelectronics Development Challenges
Webinar - May 10, 2022 by Rich Powlowsky
In this session, you will learn how Siemens is a full solution provider to the fabless design community, including SoCs and Heterogeneous Integration from concept through GDSII sign off, through to the manufactured wafer and product life cycle.
-
Bringing Model-based Systems Engineering to IC and FPGA Design
Webinar - May 10, 2022 by Ray Salemi
In this session, you will learn how international competition has forced the change, how model-based design will change the way the Defense Industrial Base works with the DoD, and what all this means for IC verification.
-
From Model to Implementation with High-Level Synthesis
Webinar - May 10, 2022 by Russell Klein
In this session, you will learn how HLS can enable system verification in an MBSE flow, and how HLS can mitigate supply chain risks.
-
Accelerate Learning Curves and Achieve Program Goals Efficiently
Webinar - May 10, 2022 by Chris Giles
In this session, you will learn how Questa Design Solutions accelerates development learning and improves and instruments development efficiency by providing design quality insight early, then monitoring throughout development.