Topics tagged sequence

Topic	Replies	Views	Activity
Flow control dependency in a sequence (or virtual sequence) on events monitored on other interface in IP UVM UVM , sequence , UVM-virtual_sequences , flow_control	3	733	February 22, 2021
Get coverage and send a new sequence if the goal is not reached UVM UVM , Coverage , sequencer , sequence	2	574	January 15, 2021
Generic sequence call on different sequencers UVM UVM , sequence , sequncer , UVM-virtual_sequences	3	1472	November 10, 2020
How to use two different agents in UVM for read and write interfaces with independent clocks? UVM UVM , sequence , agents	4	1080	October 6, 2020
Can we extend seq_item or sequence in test class? UVM UVM , sequence , testcase , sequence_item	3	760	September 29, 2020
Sequencer UVM UVM , sequencer , sequence	9	1978	September 28, 2020
How to write a UVM Sequence UVM SystemVerilog , UVM , sequence , uvm-sequence-item	3	1984	August 11, 2020
Connecting Sequence to Scoreboard UVM UVM , sequence , analysis-port , UVM-scoreboard	6	3143	August 10, 2020
Stop Sequence UVM UVM , sequence , raise-objection , testcase	2	938	August 6, 2020
Start_item in sequence UVM UVM , sequence	6	9337	July 24, 2020
Uvm_sequence UVM UVM , sequence	1	930	May 8, 2020
Wait_for_item_done() is still in wait state even after item_done() is hit UVM UVM , sequence , item_done , wait_for_item_done	1	1843	April 27, 2020
Sequence in UVM UVM UVM , sequence , interface , posedge-clk-begin , wait-statement	5	1187	April 22, 2020
Doubt in property block (SystemVerilog Assertion) SystemVerilog SystemVerilog , SVA , sequence , assert-property	1	1002	April 1, 2020
Implement transaction logic in driver or sequence class UVM UVM , sequence , driver	12	1701	April 1, 2020
How to pause a sequence based on event UVM UVM , sequence , Cookbook-SequencesVirtualSequencer , systemverilog-uvm , sequence-arbitration , sequencer-arbitration	11	2689	March 12, 2020
Number of outstanding sequences on an UVM sequencer UVM UVM , sequence	3	1072	January 22, 2020
Using uvm_component to create sequences UVM UVM , sequence , macros , uvm_component	4	1465	January 20, 2020
Regarding Sequence issue related to UVM1.2 UVM UVM , sequence , UVM_INFO-packet_sequencesv38--0-uvm_test_topeagseqrpacket_sequence-TRACE-unitpacket_sequencebody-wait-grant , UVM12	4	1167	January 7, 2020
How to handle complex bus sequences using the Register Layer UVM UVM , sequence , register-layer , adapter	5	2174	November 21, 2019
How to make addresses randomised in write sequence and read sequence are same UVM SystemVerilog , UVM , sequence	1	823	September 30, 2019
User defined variable UVM UVM , sequence , randomization , Transaction , User-defined-variable	1	1021	September 10, 2019
Use `uvm_do macro from uvm_test UVM UVM , sequence , UVM-uvm_test , uvm_do-macros	9	3741	July 24, 2019
Dont drive a value to virtual interface in uvm driver UVM UVM , error , sequence , driver , virtual	5	1706	June 25, 2019
Stop and restart assertion from sequence UVM UVM , sequence , assertoff , asserton	2	1571	May 8, 2019
What is the right methodology to write a register check? UVM UVM , Cookbook-Registers , sequence , checker , Methodology , Checkers	7	3943	January 29, 2019
Config Objects in sequences UVM UVM , sequence , config-object	7	4440	January 26, 2019
Factory over-ride mechanism for sequence UVM UVM , sequence , VIP , factory-overrides	3	1327	September 20, 2018
Start_item in sequence UVM UVM , sequence	1	1293	August 1, 2018
Get the status of a sequence UVM UVM , sequencer , sequence , driver	6	3375	July 30, 2018