Hi all,here I have a typical code for transaction of single sequence where the number of transaction is 10.I want to give the access of user to give any value lets no_of_variable at the top level derived class of uvm_test and that will control that many number of transaction in the sequence.
Any suggestion would be appreciated.Thanks.
//================= code starts here =================//
//=============== multiple transaction exp2 ================//
//multiple transaction are done between sequencer to driver
`include "uvm_macros.svh"
package my_pkg;
import uvm_pkg::*;
//sequence_item class
class my_transaction extends uvm_sequence_item;
`uvm_object_utils(my_transaction)
rand logic [3:0] a;
rand byte b;
constraint c_a {a>5;a<15;}
constraint c_b {b>0;b<10;}
function new(string name = "");
super.new(name);
endfunction
endclass
//sequence class
class my_sequence extends uvm_sequence #(my_transaction);
`uvm_object_utils(my_sequence)
my_transaction req;
function new(string name = "");
super.new(name);
endfunction
task body();
repeat(10) begin
req=my_transaction::type_id::create("req");
start_item(req);
if (!req.randomize()) begin
`uvm_error("MY_SEQUENCE", "Randomize failed.");
end
//$display("a=%0d b=%0d",req.a,req.b);
`uvm_info("my_sequence",$sformatf("a=%0d b=%0d",req.a,req.b),UVM_MEDIUM)
finish_item(req);
end
endtask
endclass
class driver extends uvm_driver #(my_transaction);
`uvm_component_utils(driver)
function new(string name,uvm_component parent=null);
super.new(name,parent);
endfunction
task run_phase(uvm_phase phase);
`uvm_info(get_type_name(), "in run_phase", UVM_MEDIUM)
forever begin
seq_item_port.get_next_item(req);
//#10; //time is optional,recommended to put
seq_item_port.item_done;
end
endtask
endclass
//test class
class my_test extends uvm_test;
`uvm_component_utils(my_test)
function new(string name,uvm_component parent=null);
super.new(name,parent);
endfunction
my_sequence seq;
driver div;
uvm_sequencer #(my_transaction) ss;//as no manual sequencer is required
function void build_phase(uvm_phase phase);
seq=my_sequence::type_id::create("seq");
ss=uvm_sequencer#(my_transaction)::type_id::create("ss",this);
div=driver::type_id::create("div",this);
endfunction
function void connect_phase(uvm_phase phase);
div.seq_item_port.connect(ss.seq_item_export);
endfunction
task run_phase(uvm_phase phase);
phase.raise_objection(this);
begin
seq.start(ss);
end
phase.drop_objection(this);
endtask
endclass
endpackage : my_pkg
module tb();
import my_pkg::*;
import uvm_pkg::*;
initial begin
run_test("my_test");
end
endmodule
//====================== END =========================//