Doubt in property block (SystemVerilog Assertion)

SystemVerilog
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1

Here is a code--------
sequence s27a;
©(posedge elk) a##[l:2] b;
endsequence

sequence s27b;
©(posedge elk) c##[2:3] d;
endsequence

property p27;
©{posedge elk) s27a and s27b;
endproperty
a27: assert property(p27);

can property p27 block written as follows??

property p27;
s27a and s27b;
endproperty

Will it give same results?? Kindly help

2

In reply to aman62:
Yes becuae each of the sequence have their own clocking events.
Ben