Topics tagged ral

Topic	Replies	Views	Activity
Question related to RAL methods SystemVerilog UVM , RAL , uvm_ral , RAL-UVM	0	291	February 26, 2024
How to access UVM_MEM using the .write method UVM UVM , RAL , uvm_mem	2	440	February 25, 2024
UVM RAL Memory - Sampling after read/write operation UVM SystemVerilog , Coverage , RAL , uvm_mem , Sampling	0	478	February 3, 2024
My question is how to verify “R0” (Read only) registers through backdoor or front door mechanism ? In frontdoor usually we do masking of RO registers to not to write .If RO register is designed with bug with RW type how to verify this issue without write UVM RAL	1	364	January 23, 2024
In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor? UVM UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	0	311	December 29, 2023
Access (to W/R) 2 Specific fields in a 32-bit register UVM RAL , uvm-ral , Systemverilog-UVM-RAL	1	314	December 27, 2023
RAL Integration UVM UVM , RAL , APB , vip-intergrate , register_model	0	395	December 11, 2023
I had an issue regarding RAL, i am unable to create a map which should contains maps of different invidual registers UVM UVM , RAL , RAL-UVM	0	321	December 6, 2023
Predicting Read Only Register in RAL UVM UVM , RAL , prediction-monitor-scoreboard , predictors	1	758	November 30, 2023
How to do Scoreboarding or checking the WR_data and read data matching in RAL UVM UVM , RAL	1	394	November 29, 2023
How to set a register to a value thru a hierarchy receiving as string? UVM UVM , RAL , accessing-the-associative-array-elements , systemverilog-Arrays	3	633	October 4, 2023
Environment and DUT random configuration UVM UVM , RAL , configuration , randomization , UVM-Environment	7	630	September 25, 2023
IN UVM RAL Adapter class, why do we use const ref for uvm_bus_reg_op in reg2bus and only ref for uvm_bus_reg_op in bus2reg? UVM UVM , RAL , adapter	1	323	August 25, 2023
Info regarding built in sequences for memory UVM UVM , RAL	6	689	May 23, 2023
What is the purpose of bus_req.end_event.wait_on(); in uvm_reg_map::do_bus_write UVM UVM , RAL	1	517	March 21, 2023
RAL: set_check_on_read(1) does not work with frontdoor access and passive prediction? UVM UVM , RAL , auto-prediction , set_check_on_read	0	660	March 9, 2023
DUPIDN compilation error for reg models UVM UVM , RAL , RAL-IPXACT , UVM-UVMRAL	0	355	February 27, 2023
UVM RAL sequences with priority UVM UVM , RAL , sequence-arbitration , sequencer-arbitration , UVM-RAL-SEQUENCE	4	875	February 15, 2023
Invalid Register access UVM UVM , RAL , uvm-register-model , -UVM-warnings-disable	4	865	February 6, 2023
How to get uvm_reg_file instance by name in uvm_reg_block UVM UVM , RAL , uvm_ral	0	430	January 9, 2023
Write '1' and '0' is not happening while running bit bash sequence UVM UVM , RAL , UVM-bit_bash	1	554	January 2, 2023
How to implement $sformatf on register models UVM UVM , assertion , RAL	6	753	December 21, 2022
Register Backdoor Issue UVM UVM , RAL , Cookbook-RegistersBackdoorAccess , UVM-RAL-Backdoor-Write-hdl_path	3	4074	November 4, 2022
How to find, if register model is updated or not UVM UVM , RAL	0	417	August 19, 2022
A resource with meta characters in the field name has been created "m_regmod " UVM UVM , RAL , uvm_ral	0	821	July 13, 2022
RAL read and auto_predict UVM UVM , RAL	0	587	May 4, 2022
Hanging register write UVM UVM , RAL , Write , hang , UVM_IS_OK	1	564	April 16, 2022
Combining all reg_models into one UVM UVM , RAL , systemverilog-uvm , UVM-RAL-UVM	3	1069	March 7, 2022
RAL read and write issues to Design UVM UVM , RAL , RAL-UVM	9	1496	March 7, 2022
Functions inside apb adapter are not being called from the test sequence UVM UVM , RAL , RAL-UVM , uvmral	2	763	February 23, 2022