One register map for multiple agents?

UVM
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1

so my design have a register layer that can be accessed from two different interfaces of the DUT. The address mapping is identical for both interfaces. Each interface has an agent for it, and the agent contains an adapter to translate register sequence item to/from bus sequence item.

The question is, how can I use the same regmap for multiple adapters? Since the address mapping is the same for both interfaces, adding an identical regmap into reg block sounds redundant and could be costly if the reg block gets big.

2

In reply to soloist_huaxin:

I think it’s not possible as you can have only one set of sequencer and adapter associated with a register map.

// CLASS: uvm_reg_map
// has below method to set sequencer and adapter associated with the map and 
// it must be called before starting any sequences based on uvm_reg_sequence.
virtual function void set_sequencer (
  uvm_sequencer_base sequencer,  
  uvm_reg_adapter adapter = null
)

Whereas, advantage of two identical register maps for both the interface is,

  • When you make one side of agent passive, you can enable only register value
    prediction through bus monitor on that interface.
  • Scenarios such as ‘Writing to same/different register from both interface at same time’ can be created.
  • As both interface might be having different protocols, its better to have separate register maps.
3

In reply to soloist_huaxin:
Hi,
It can be done while using uvm_reg_frontdoor (user defined frontdoor) mechanism and using reg.set_frontdoor() function.

Here is code of uvm_reg_frontdoor:


//------------------------------------------------------------------------------
// Class: uvm_reg_frontdoor
//
// Facade class for register and memory frontdoor access.
//------------------------------------------------------------------------------
//
// User-defined frontdoor access sequence
//
// Base class for user-defined access to register and memory reads and writes
// through a physical interface.
//
// By default, different registers and memories are mapped to different
// addresses in the address space and are accessed via those exclusively
// through physical addresses.
//
// The frontdoor allows access using a non-linear and/or non-mapped mechanism.
// Users can extend this class to provide the physical access to these registers.
//
virtual class uvm_reg_frontdoor extends uvm_reg_sequence #(uvm_sequence #(uvm_sequence_item));

   // Variable: rw_info
   //
   // Holds information about the register being read or written
   //
   uvm_reg_item rw_info;

   // Variable: sequencer
   //
   // Sequencer executing the operation
   //
   uvm_sequencer_base sequencer;

   // Function: new
   //
   // Constructor, new object given optional ~name~.
   //
   function new(string name="");
      super.new(name);
   endfunction

   string fname;
   int lineno;

endclass: uvm_reg_frontdoor

Extend this class and make your own 2 frontdoor class

class my_fd_1 extends uvm_reg_frontdoor;

  function new (string name = "my_fd_1");
    super.new(name);
  endfunction : new

  `uvm_object_utils(my_fd_1)

endclass : my_fd_1

Same way to my_fd_2 and instantiate those in your environment , then assign respective sequencer and adapter to these frontdoors.

In ENV:

class env extends uvm_env;

  //-- variable declarations
  my_fd_1 fd1; // user defined frontdoor mechanism
  my_fd_2 fd2;

  // adapter
  my_adapter_1 adptr1;
  my_adapter_2 adptr2;

  // agent
  my_agent1  agent1;
  my_agent2  agent2;

  //---
  function void build_phase (uvm_phase phase);
    // agent and adapter creation
    fd1 = my_fd_1 :: type_id :: create("fd1",this);
    fd1 = my_fd_2 :: type_id :: create("fd2",this);

    // assign adapter to frontdoor
    fd1.adapter = adptr1;
    fd2.adapter = adptr2;

  endfunction : build_phase

  // connect phase
  function void connect_phase (uvm_phase phase);
    // assign respective seqrs
    fd1.sequencer = agent1.seqr;
    fd2.sequencer = agent2.seqr;
  endfunction : connect_phase

endclass : env

Now, How to initiate register read and write request by using frontdoor
If you want to generate physical request through agent1.seqr then use fd1 frontdoor mechanism by putting below code before write/read task of register in sequence.

 //sequence task of register write 
 task reg_write();
 // ----
 // set frontdoor for below write request
  reg.set_frontdoor( .ftdr(p_sequencer.env.fd1) // set frontdoor fd1
                     .map(reg_model.reg_map));  // your single register map

reg.write(//--);

endtask : reg_write

same way for read operation.

Let me know if have any confusion.

4

In reply to kerulmodi:


  reg.set_frontdoor( .ftdr(p_sequencer.env.fd1) // set frontdoor fd1
                     .map(reg_model.reg_map));  // your single register map

Seems I am missing something. How in sequence we are getting env handle ?
Usually env handle is available in tests only instead of sequence isn’t it?

5

In reply to bhupesh.paliwal:

Ya thats correct but you can use environment handle via p_sequencer handle.


//  Make sure your sequencer is having env handle.
p_sequencer.env

Regards,
Kerul Modi