Topics tagged hierarchy

Topic	Replies	Views	Activity
Using non-UVM agents in a UVM environmet UVM UVM , hierarchy , configdb , agent	1	1353	March 28, 2024
Best way to dynamically access the same hierarchy cell in another module SystemVerilog SystemVerilog , hierarchy , hierarchy-reference	0	239	March 9, 2024
Accessing a generate block hierarchachy SystemVerilog SystemVerilog , hierarchy , genvar	5	2168	September 7, 2021
Question on the use of interfaces to bundle up vectors SystemVerilog SystemVerilog , hierarchy , interface	1	657	July 14, 2021
Hierarchical access to a coverpoint from interface UVM SystemVerilog , UVM , Coverage , hierarchy , interface	1	873	January 16, 2021
Variable in Hierarchical access SystemVerilog SystemVerilog , hierarchy , macros , DUT-parameters	2	2524	September 13, 2019
Checking for register state changes immediately after release of reset (removal violations) SystemVerilog SystemVerilog , hierarchy , reset , cher	1	788	March 28, 2019
Functional Coverage: Sampling RTL signals in a hierarchy (gives error) SystemVerilog SystemVerilog , functional-coverage , hierarchy	2	3698	February 19, 2014