Best way to dynamically access the same hierarchy cell in another module

SystemVerilog
, ,
1

Hi, all. I am working on a variant system where I am running two identical modules under the testbench. The only difference between these two modules is some unique data in the memory.

module Top();

MAGIC_AND c1(A, B, O, O_diff);

endmodule

module Testbench();

Top dut();
Top variant();

endmodule


module MAGIC_AND(
    input A,
    input B,
    output O,
    output O_diff
);
    assign O = A & B;
    if (under variant)
        O_diff = 0;
    else // under dut
        O_diff = O ^ Testbench.variant.c1.O;

endmodule

I am planning to create a MAGIC cell that can gather the value of dut.c1.O and variant.c1.O, and produce an alert if they are not the same. However, I am facing a challenge since I am working on a netlist with thousands of cells. I am wondering if there is any way to access the same hierarchy cell in another module.

Thanks.