Accessing a generate block hierarchachy

SystemVerilog
, ,
1

I tried to access the signal within a module instantiated through gen block.

But I am receiving the below error

Implicit name not allowed in a hierarchical name

2

In reply to harshit1027:

Without seeing any code, it is impossible to provide any advice.

3

In reply to cgales:
module adder(input a, input b)
#####code
endmodule

module full_adder(input c, input d);
generate
for (genvar temp=0; temp < 1; temp++)
for (genvar t1=0; t1< 2 ; t1++)
adder add(a,b);
endgenerate
endmodule

module run_adder;

full_adder f1(c,d);

endmodule

Now I want to access signals within the adder module, how to do that??

4

In reply to harshit1027:

Please provide a complete example that shows the error you are receiving.

Your code doesn’t compile, and there is no attempt to reference any signal within ‘adder’, so I’m not sure in what context you are trying to use these signals.

5

In reply to cgales:

Explicitly name your generate iterative blocks.

module adder();
  wire foo;
endmodule

module full_adder();
  for( genvar i = 0; i < 1; i++ )
  begin : iter_i
    for( genvar j = 0; j < 2; j++ )
    begin: iter_j
      adder add();
    end
  end
endmodule

module top;
  full_adder f1();
  wire foo_0_0 = f1.iter_i[0].iter_j[0].add.foo;
  wire foo_0_1 = f1.iter_i[0].iter_j[1].add.foo;
endmodule

Unchecked, but should be close.

6

In reply to Mark Curry:

Thanks, now explicitly naming iterative blocks resolved the issue