In reply to cgales:
module adder(input a, input b)
#####code
endmodule
module full_adder(input c, input d);
generate
for (genvar temp=0; temp < 1; temp++)
for (genvar t1=0; t1< 2 ; t1++)
adder add(a,b);
endgenerate
endmodule
module run_adder;
full_adder f1(c,d);
endmodule
Now I want to access signals within the adder module, how to do that??