Accessing a generate block hierarchachy

SystemVerilog
, ,
5

In reply to cgales:

Explicitly name your generate iterative blocks.

module adder();
  wire foo;
endmodule

module full_adder();
  for( genvar i = 0; i < 1; i++ )
  begin : iter_i
    for( genvar j = 0; j < 2; j++ )
    begin: iter_j
      adder add();
    end
  end
endmodule

module top;
  full_adder f1();
  wire foo_0_0 = f1.iter_i[0].iter_j[0].add.foo;
  wire foo_0_1 = f1.iter_i[0].iter_j[1].add.foo;
endmodule

Unchecked, but should be close.