Topics tagged DUT-parameters

Topic	Replies	Views	Activity
Passing TB/RTL parameters to sequences UVM UVM , DUT-parameters , ParameterizedClass	3	1148	November 14, 2020
Variable in Hierarchical access SystemVerilog SystemVerilog , hierarchy , macros , DUT-parameters	2	2570	September 13, 2019
Access internal module signals via bind if internal signals depends on generate block SystemVerilog SystemVerilog , bind , binding-in-SV , DUT-parameters	0	2217	October 21, 2018
Race condition setting config from testbench parameter UVM UVM , testbench , uvm_config_db , DUT-parameters	3	2346	August 1, 2016
Changing the DUT parameters UVM UVM , DUT-parameters	3	4814	May 5, 2016