Topics tagged genvar

Topic	Replies	Views	Activity
How to use generate block in top module in UVM UVM UVM , generate , genvar , clockgeneraation , systemverilog-generate , system-verilog-interface-generate	5	683	June 12, 2023
Accessing a generate block hierarchachy SystemVerilog SystemVerilog , hierarchy , genvar	5	2194	September 7, 2021
Uniqe assertion label name SystemVerilog SystemVerilog , genvar	6	2693	February 27, 2018
Is hierarchical reference to the loop index variable in a for loop generate block possible? SystemVerilog SystemVerilog , generate-block , hierarchical-reference , genvar	1	4613	November 13, 2014