How to use generate block in top module in UVM

UVM
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1

Hi,

I am trying to use genvar and genrate block in top module of the UVM. I took three clocks and I want to connect to the common clock I tried using generate block but I am getting some syntax error I am unable to find where I made the mistake can anyone please help me to resolve this issue.
Note:
I have 3 modules I want to connect common clock to the 3 Modules

I am sending the eda code link along with error messsage
Eda Playground link:
IRQ IN AND IRQ OUT AGENT(1) - EDA Playground

Error:

Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 31: token is ‘[’
mpu_clock[i] = clk;

Thanks in Advance
Harshavardhan ^

2

In reply to Harsha vardhan:

You never declared mpu_clock in the testbench.sv module.

3

Hi,
please check in this code

4

In reply to Harsha vardhan:

On line 13 I added to the declaration:

bit mpu_clock1,mpu_clock2,mpu_clock3, mpu_clock[1:3];

The generate block creates code, but it still needs to be legal. You can’t just have “signal0 = signal1;” in the middle of a module. I changed line 31 to the following continuous assignment. The testcase compiled successfully and ran.

assign mpu_clock[i] = clk;

By the way, don’t include a package, import it, and only inside a module, interface, or another package.

5

Hi chrisspear,

Thanks for the help now my code is running with out any errors but now I am not able to see the mpu_clock1,mpu_clock2,mpu_clock3 similar like clk signal, I am observing only zero value ifor the above 3 signals can you please help how I can get all the mpu_clock signals similar like my clk signal.

Thanks in Advance,
Harshavardhan

6

In reply to Harsha vardhan:

Your original code had 3 scalar signals, mpu_clock1,mpu_clock2,mpu_clock3. Then you added the vector mpu_clock[3], and we connected it. Why do you want to go back to the scalars?

Also, why do you have a generate statement? You hardcoded the for-loop bounds and used 5 lines to write what could have been done in 3. Plus it mixes procedural code with signals. Your original code was:

genvar i;
  initial
    begin
//  genvar i;
    generate
      repeat(clk) // This does not make sense
        begin
      for(i=1; i<=3; i++)
     begin
       
   //    always @(posedge clk)
      //   begin
  assign mpu_clock[i] = clk;
     //  $display("count for generate block is %0d",count[i]);
         end
     //end
    endgenerate
    end

You can simplify this to the following, no generate, no initial:


  assign mpu_clock[1] = clk;
  assign mpu_clock[2] = clk;
  assign mpu_clock[3] = clk;