Can I register a non UVM agent in the uvm environment?
If so how?
Specifically I’m trying to integrate Xilinx axi_vip (for a Zynq design) into a UVM environment.
Since it is not a UVM object it has no create method…
I can new the agent in the environment build phase, but I’m having trouble connecting the Interface into the VIP hooks in the DUT.
I suspect that part of this is I’m not registering the agent with the db, but I’m not clear on how to do that exactly.
Thanks,
David
Apologies for necro-posting,
I’ve currently been trying to do a similar thing although the class at hand was not a component but rather an object.
We know that SystemVerilog doesn’t support multiple inheritance, but we also know that we can kind of ‘fake it’ through the usage of ‘mixin’ class. There’s an interesting article on mixin classes here: Fake It ‘til You Make It - Emulating Multiple Inheritance in SystemVerilog | Verification Gentleman Blog
Although the article is very well written it comes short on one aspect, but it’s highlighted in one of the comments:
The problem is that the mixin’s constructor must call super.new() on its parameter/ancestor class, and therefore must know the signature of that class’s constructor. This, of course, severely restricts the set of classes to which the mixin can be applied. Similarly, the mixin’s constructor must have a signature matching its parameter/ancestor, otherwise anything derived from the mixin will get a nasty surprise when trying to call super.new().
Therefore if your class doesn’t have a constructor that has the same signature as the uvm class you want it to mix with, then you are out of luck cause SystemVerilog doesn’t support function/task overloading either and I’m still trying to find a solution for that.
If in the meantime you can share what you did back then, it would be very helpful.
Cheers