Assigning a bit in SV Assertion

In reply to ben@SystemVerilog.us:

In reply to ben@SystemVerilog.us:
// another option
property data_check;
@(clk) @rose(write_cycle) |->
first_match(##[1:5] signal_to_check == write_data) ##1
((signal_to_check == write_data)[*1:$] ##1 $rose(write_cycle));
endproperty


Ben systemverilog.us



Hi Ben,

I intentionally rewrote the assertion as below:
property data_check;
@(clk) @rose(write_cycle) |->
 first_match(##[1:5] signal_to_check == write_data) |->
 ((signal_to_check == write_data) until $rose(write_cycle));
endproperty

**initial $assertvacuousoff(0);**

**assert property (data_check) $display ("Assertion Pass") else $error();**

**and forced the "signal_to_check" to 0** in the testcase. Now this is a case of vacuous success and the pass block should have been turned off. But still the pass block remains on. Why this kind of behaviour?