In reply to ben@SystemVerilog.us:
Hi Ben,
Finally decided to go with the clock. I wrote the assertion as below:
property data_check;
@(clk) @rose(write_cycle) |-> ##[1:5] first_match(signal_to_check == write_data) |-> ((signal_to_check == write_data) until $rose(write_cycle));
endproperty
Basically I want that when the bit write_cycle goes high, the check should begin when the first match occurs and should continue till the next rise of the bit write_cycle.
To check the assertion I forced “signal_to_check” to be zero. Still the assertion passes. Seems to be a vacuous pass. What could be the reason here?