Assigning a bit in SV Assertion

In reply to ben@SystemVerilog.us:

To avoid vacuity after the rise of the write, use the followed-by operator that represents a sequence followed by a property



property data_check;
@(clk) @rose(write_cycle) |->
 first_match(##[1:5] signal_to_check == write_data) #-# 
((signal_to_check == write_data) until $rose(write_cycle));
endproperty

// another option 
property data_check;
@(clk) @rose(write_cycle) |->
 first_match(##[1:5] signal_to_check == write_data) ##1
 ((signal_to_check == write_data)[*1:$] ##1 $rose(write_cycle));
endproperty

Ben systemverilog.us