Assigning a bit in SV Assertion

The intent of using an always_comb block is to ensure the comparison happens independent of any clock.

You have a clocked system. There is NO treason to have a continuous check between clocking events.


// Check that comparison which was written inside the first_match() 
//    remains valid until the next write_cycle is detected
ap_found_compare: assert property(@ (posedge clk)
  (match_found) |-> comparision_statemen );   

Ben SystemVerilog.us