Assigning a bit in SV Assertion

In reply to atanu.biswas:

So the issue is that if there is some glitch sampled by the RTL at that high frequency clock, I fear that the assertion wont be able to catch it. Hence to make it fool proof I am using the always_comb block for the data check.

I don’t see how the always_comb prevents any glitch in the signal from triggering a false error. Maybe I am missing something here. SVA allows for multiclocking. For example:


ap_found_compare: assert property(@ (posedge clk1)
  (match_found) |-> @ (posedge clk2)comparision_statement );  

In your testbench environment you could construct a safe clk2 to do your sampling of the comparision_statement. That build of clk2 could be combinational logic, or simply a delayed (e.g., # 2ns) off a known clock.
an always_comb triggers at every change of signals in the block, including glitches.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


  1. SVA Alternative for Complex Assertions
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  2. SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  3. SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment