In reply to atanu.biswas:
So the issue is that if there is some glitch sampled by the RTL at that high frequency clock, I fear that the assertion wont be able to catch it. Hence to make it fool proof I am using the always_comb block for the data check.
I don’t see how the always_comb prevents any glitch in the signal from triggering a false error. Maybe I am missing something here. SVA allows for multiclocking. For example:
ap_found_compare: assert property(@ (posedge clk1)
(match_found) |-> @ (posedge clk2)comparision_statement );
In your testbench environment you could construct a safe clk2 to do your sampling of the comparision_statement. That build of clk2 could be combinational logic, or simply a delayed (e.g., # 2ns) off a known clock.
an always_comb triggers at every change of signals in the block, including glitches.
Ben Cohen
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment