Assigning a bit in SV Assertion

In reply to atanu.biswas:

Your assertion looks OK to me. See my reply on SV evaluation regions.
https://verificationacademy.com/forums/systemverilog/sampling-point-assertions

Your function changes the value of your variable in the Observed region, way past the Preponed region where the signals are sampled.
I didn’t understand your last explanation.
Ben systemverilog.us