In reply to atanu.biswas:
An assertion is attempted at every clocking event. Read my paper on the modeling of an assertion using SV only.
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy
If you understand the fork join_any and tasks, then you’ll understand the modeling of an assertion, including the concept of antecedent / consequent and why you have errors without the implication operator.
Ben Ben@systemverilog.us