Assigning a bit in SV Assertion

SystemVerilog
, , ,
21

Hi Ben,

In the below property I am trying to make some assignment as shown below after $rose(write_cycle):

property data_check;
logic [15:0] temp_data1, temp_data2;
@(clk) (@rose(write_cycle), 
 **if (condition1)
    temp_data1 = //something
  else if (condition2)
    temp_data2 = //something
  else
    //something else**
 ) |->
 first_match(##[1:5] signal_to_check == write_data) ##1
 ((signal_to_check == write_data)[*1:$] ##1 $rose(write_cycle));
endproperty

Is this the correct way to do it? I am getting syntax errors