In reply to atanu.biswas:
// property ::=
// if (expression_or_dist) property_expr1
//. else property_expr2
// **** following is illegal
// you have
A_property |-> b_property
// above is not a property.
// study the syntax and operators for properties & sequences
property data_check; // **** following is illegal
logic [15:0] temp_data1, temp_data2;
@(clk) (@rose(write_cycle),
if (condition1)
temp_data1 = //something
else if (condition2)
temp_data2 = //something
else
//something else
) |->
first_match(##[1:5] signal_to_check == write_data) ##1
((signal_to_check == write_data)[*1:$] ##1 $rose(write_cycle));
endproperty
Ben systemverilog.us