In reply to ben@SystemVerilog.us:
In reply to ben@SystemVerilog.us:
To avoid vacuity after the rise of the write, use the followed-by operator that represents a sequence followed by a property
// another option
property data_check;
@(clk) @rose(write_cycle) |->
first_match(##[1:5] signal_to_check == write_data) ##1
((signal_to_check == write_data)[*1:$] ##1 $rose(write_cycle));
endproperty
I have one more query. I am using the above mentioned assertion. I am asserting the property as below:
assert property (data_check) $display (“Assertion Pass”); else error
But the pass statement is not showing up on each and every clock edge at which the assertion passes. Instead it shows up only once. Dont know the reason for this.