In reply to atanu.biswas:
You are incorrectly applying the first_match
Should be
property data_check;
@(clk) @rose(write_cycle) ##0 first_match(##[1:5] signal_to_check == write_data) |-> ((signal_to_check == write_data) until $rose(write_cycle));
endproperty
- you don’t need the |-> after the 1st rose because if there is no match then the assertion is vacuous.
- ##[1:5] first_match(expr) is same as
##[1:5] expr because expr sequence is of one cycle.
Actually it is ##1 first_match(expr) or ##2 first_match(expr) or…
Whereas first_match(##[1:5] expr) picks the 1st match of the sequence (##[1:5] expr)
Thus, it picks the first_match of the sequence
##1 expr or ##2 expr or… ##5 expr.
Ben systemverilog.us